چکیده مقاله
Floating point numbers are utilized in the digital application like modern computers, embedded processors, digital signal processors, digital filters and signal processing application real numbers in binary format are represented by Floating point numbers arithmetic operations with floating point numbers FPN are commonly executed using hardware In this paper, we propose architectures for performing addition, subtraction, multiplication, division and the square root of floating point numbers using the IEEE 754 standard these architectures are designed using VHDL Hardware Description Language HDL and are implemented on Cyclone IV EP4CE30F23C7 FPGA In this implementation, we try to use from simple units Multiplexer, comparator, add/sub have been used in this implementation to reduce the numberof resources used
کلیدواژهها
نویسندگان
Reza Eyvazpour
Department of Electrical and Computer Engineering, Tabriz University, Tabriz, Iran,
Behzad Nobahar
Department of Electrical and Computer Engineering, Tabriz University, Tabriz, Iran,
Najme Permeh
Department of Electrical and Computer Engineering, Tabriz University, Tabriz, Iran,
شیوه ارجاع
Eyvazpour, Reza and Nobahar, Behzad and Permeh, Najme,1398,FPGA-based implementation of Single Precision Floating Point Arithmetic operation,Sixth National Congress on Electrical Engineering and Computer Engineering of Iran with a New Approach to New Energy,Tehran
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