چکیده مقاله
In this paper a new optimization method is proposed for transistor sizing of VLSI digital circuits based on artificial intelligence The optimized dimensions are especially conducted for minimizing power dissipation dynamic and static power and delay In order to verify the efficiency of the proposed method, transistor’s dimensions of four well known full adder circuits in different frequencies and voltage levels are optimized and their results are compared to the previously reported results Simulation results of HSpice provided in TSMC 0 18μm technology, show considerable improvement of power delay product PDP reduction The results promise a strong impact since full adders are the basic block in the most VLSI circuits
کلیدواژهها
نویسندگان
Eghbal Rahimi
Department of Electrical Engineering, Khorasan Razavi Science and Research Branch Islamic Azad University, Neyshabur, Iran
Seyyed Reza Talebiyan
Department of Electrical Engineering, Imam Reza International University, Mashhad, Khorasan Razavi, Iran
شیوه ارجاع
Rahimi, Eghbal and Talebiyan, Seyyed Reza,1394,A Novel Method for Transistor Sizing in Digital Circuits by Artificial Intelligence,International Conference on New Research Findings in Electrical Engineering and Computer Science,Tehran
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