Seyyed Reza Talebiyan

Design of New High-Performance Full Adder Using Hybrid-CMOS Logic Style for High-Speed Applications

This paper, presents a new design for 1 bit full adder cell using hybrid CMOS logic style Using a novel…

A Novel Method for Transistor Sizing in Digital Circuits by Artificial Intelligence

In this paper a new optimization method is proposed for transistor sizing of VLSI digital circuits based…

Novel Design of Array Multiplier

In this paper a new array multiplier has been proposed, which has lower power consumption than the regul…