چکیده مقاله
Technology scaling has brought forth major issues related to process variation such as circuit stability and reliability degradation, which are especially problematic for the Static Random Access Memories SRAM As we know SRAM occupies the majority of the die area in system on chips and microprocessors Because of Low operating voltage, small node capacitance, high packing density, and lack of error masking mechanisms memories are more vulnerable to soft error This paper propose a new hardening design for an 14 transistors 14T cmos memory cell at 32nm feature size the proposed hardened memory cell overcome the circuit stability problem of previous design by utilizing separate bit lines for read and write operation The simulation results show that the 14T cell has better stability and lower power consumption in compare to recent reported designs In addition the proposed cell exhibits 36% larger critical charge than the conventional design
کلیدواژهها
نویسندگان
LEILA MORAD
Technical Engineering Department, University of Mohaghegh Ardabili, Ardabil, Iran
JAVAD JAVIDAN
Technical Engineering Department, University of Mohaghegh Ardabili, Ardabil, Iran
GHOLAMREZA ZARE FATIN
Technical Engineering Department, University of Mohaghegh Ardabili, Ardabil, Iran
EHSAN MORAD
Department of Electrical Engineering, Islamic Azad University,Sience and Research, Tehran Branch, Tehran, Iran
شیوه ارجاع
MORAD, LEILA and JAVIDAN, JAVAD and ZARE FATIN, GHOLAMREZA and MORAD, EHSAN,1394,A Novel Soft Error Hardened 14T SRAM Cell,International Conference on New Research Findings in Electrical Engineering and Computer Science,Tehran
ارائهشده در
مجموعه مقالات سومین کنفرانس ملی محاسبات نرم علوم مهندسی در صنعت و جامعه1 اسفند 1402 · ایرانشهر