چکیده مقاله
This paper, presents a new design for 1 bit full adder cell using hybrid CMOS logic style Using a novel structure for implementation of the proposed full adder caused it has better performance in terms of propagation delay and power delay product PDP compared to its counterparts According to the simulation results, the propagation delay of the proposed full adder is 22 8% less than the propagation delay of next fastest full adder, and the power delay product of the proposed full adder is 22 7% less than the next best PDP HSpice simulations using 65nm technology with a power supply of 1 2V was utilized to evaluate the performance of the circuits
کلیدواژهها
نویسندگان
Milad Jalalian Abbasi Morad
Department of Electrical Engineering, Imam Reza International University, Mashhad, Iran
Seyyed Reza Talebiyan
Department of Electrical Engineering, Imam Reza International University, Mashhad, Iran
Ebrahim Pakniyat
Department of Electrical Engineering, Imam Reza International University, Mashhad, Iran
شیوه ارجاع
Jalalian Abbasi Morad, Milad and Talebiyan, Seyyed Reza and Pakniyat, Ebrahim,1394,Design of New High-Performance Full Adder Using Hybrid-CMOS Logic Style for High-Speed Applications,International Conference on New Research Findings in Electrical Engineering and Computer Science,Tehran
ارائهشده در
مجموعه مقالات سومین کنفرانس ملی محاسبات نرم علوم مهندسی در صنعت و جامعه1 اسفند 1402 · ایرانشهر